Origin 350のセカンダリプロセッサ起動パッチを投げた

MIPS OpenBSD SMP SGI Origin

この間の起動テストコードに、CPU初期化時にセカンダリプロセッサを探してnasid, physidをstruct cpu_hwinfo secondarycpu_hwinfo[MAXCPUS]に保存し、後でこれを見に行って順に起こすというコードを足した。
でもbootcpu_hwinfoとsecondarycpu_hwinfo[]が分かれてるのはちょっとキモイよな。
と思うのでコメント求む的なメールを投げてみる。

Index: mips64/include/cpu.h
===================================================================
RCS file: /cvs/src/sys/arch/mips64/include/cpu.h,v
retrieving revision 1.58
diff -u -p -r1.58 cpu.h
--- mips64/include/cpu.h	28 Apr 2010 16:20:28 -0000	1.58
+++ mips64/include/cpu.h	18 May 2010 04:31:55 -0000
@@ -370,6 +370,10 @@ struct cpu_hwinfo {
	uint32_t	tlbsize;
	uint		type;
	uint32_t	l2size;
+#ifdef TGT_ORIGIN
+	int		nasid;
+	int		physid;
+#endif
};

struct cpu_info {
Index: sgi/include/intr.h
===================================================================
RCS file: /cvs/src/sys/arch/sgi/include/intr.h,v
retrieving revision 1.41
diff -u -p -r1.41 intr.h
--- sgi/include/intr.h	18 Jan 2010 16:59:23 -0000	1.41
+++ sgi/include/intr.h	18 May 2010 04:31:55 -0000
@@ -190,6 +190,8 @@ void	dosoftint(void);
#ifdef MULTIPROCESSOR
#if defined (TGT_OCTANE)
#define ENABLEIPI() updateimask(~CR_INT_2) /* enable IPI interrupt level */
+#elif defined (TGT_ORIGIN)
+#define ENABLEIPI() /* notyet */
#else
#error MULTIPROCESSOR kernel not supported on this configuration
#endif
Index: sgi/sgi/ip27_machdep.c
===================================================================
RCS file: /cvs/src/sys/arch/sgi/sgi/ip27_machdep.c,v
retrieving revision 1.51
diff -u -p -r1.51 ip27_machdep.c
--- sgi/sgi/ip27_machdep.c	9 May 2010 18:37:47 -0000	1.51
+++ sgi/sgi/ip27_machdep.c	18 May 2010 04:31:55 -0000
@@ -28,6 +28,7 @@
#include <sys/malloc.h>
#include <sys/reboot.h>
#include <sys/tty.h>
+#include <sys/proc.h>

#include <mips64/arcbios.h>
#include <mips64/archtype.h>
@@ -56,6 +57,10 @@ extern char *hw_prod;

extern void (*md_halt)(int);

+#ifdef MULTIPROCESSOR
+extern struct cpu_hwinfo secondarycpu_hwinfo[MAXCPUS];
+#endif
+
paddr_t	ip27_widget_short(int16_t, u_int);
paddr_t	ip27_widget_long(int16_t, u_int);
paddr_t	ip27_widget_map(int16_t, u_int,bus_addr_t *, bus_size_t *);
@@ -297,6 +302,10 @@ ip27_setup()
void
ip27_autoconf(struct device *parent)
{
+#ifdef MULTIPROCESSOR
+	int cpuid;
+#endif
+
	union {
		struct mainbus_attach_args maa;
		struct cpu_attach_args caa;
@@ -318,6 +327,15 @@ ip27_autoconf(struct device *parent)
	u.maa.maa_name = "clock";
	config_found(parent, &u, ip27_print);

+	for (cpuid = 1; cpuid < MAXCPUS; cpuid++)
+		if (secondarycpu_hwinfo[cpuid].clock != 0 
+		&& secondarycpu_hwinfo[cpuid].nasid == currentnasid) {
+			u.maa.maa_name = "cpu";
+			u.maa.maa_nasid = currentnasid;
+			u.caa.caa_hw = &secondarycpu_hwinfo[cpuid];
+			config_found(parent, &u, ip27_print);
+		}
+
	/*
	 * Now attach all nodes' I/O devices.
	 */
@@ -919,3 +937,90 @@ ip27_nmi(void *arg)
	printf("Resetting system...\n");
	boot(RB_USERREQ);
}
+
+#ifdef MULTIPROCESSOR
+
+#define LAUNCH_SLAVE \
+	(*(void (*)(int nasid, int cpu, void *call_addr, uint64_t call_parm, \
+	void *stack_addr, void *gp_addr)) PHYS_TO_CKSEG1(0x1fc00038))
+
+void
+hw_cpu_boot_secondary(struct cpu_info *ci)
+{
+	vaddr_t kstack;
+
+	kstack = alloc_contiguous_pages(USPACE);
+	if (kstack == NULL)
+		panic("unable to allocate idle stack\n");
+	bzero((char *)kstack, USPACE);
+	ci->ci_curprocpaddr = (void *)kstack;
+
+	LAUNCH_SLAVE(ci->ci_hw.nasid, ci->ci_hw.physid, hw_cpu_spinup_trampoline,
+		(uint64_t)ci, (void *)(kstack + USPACE), 0);
+
+	while (!cpuset_isset(&cpus_running, ci))
+		;
+}
+
+void
+hw_cpu_hatch(struct cpu_info *ci)
+{
+	int s;
+
+	/*
+	 * Make sure we can access the extended address space.
+	 * Note that r10k and later do not allow XUSEG accesses
+	 * from kernel mode unless SR_UX is set.
+	 */
+	setsr(getsr() | SR_KX | SR_UX);
+
+	tlb_set_page_mask(TLB_PAGE_MASK);
+	tlb_set_wired(0);
+	tlb_flush(64);
+	tlb_set_wired(UPAGES / 2);
+
+	tlb_set_pid(0);
+
+	/*
+	 * Turn off bootstrap exception vectors.
+	 */
+	setsr(getsr() & ~SR_BOOT_EXC_VEC);
+
+	/*
+	 * Clear out the I and D caches.
+	 */
+	Mips10k_ConfigCache(ci);
+	Mips_SyncCache(ci);
+
+	cpu_startclock(ci);
+
+	ncpus++;
+	cpuset_add(&cpus_running, ci);
+
+	mips64_ipi_init();
+	/* XXX: setintrmask(0) here */
+
+	spl0();
+	(void)updateimask(0);
+
+	SCHED_LOCK(s);
+	cpu_switchto(NULL, sched_chooseproc());
+}
+
+int
+hw_ipi_intr_establish(int (*func)(void *), u_long cpuid)
+{
+	return 0;
+};
+
+void
+hw_ipi_intr_set(u_long cpuid)
+{
+}
+
+void
+hw_ipi_intr_clear(u_long cpuid)
+{
+}
+
+#endif
Index: sgi/sgi/sginode.c
===================================================================
RCS file: /cvs/src/sys/arch/sgi/sgi/sginode.c,v
retrieving revision 1.19
diff -u -p -r1.19 sginode.c
--- sgi/sgi/sginode.c	6 Apr 2010 19:09:50 -0000	1.19
+++ sgi/sgi/sginode.c	18 May 2010 04:31:56 -0000
@@ -76,6 +76,10 @@ int	kl_n_mode = 0;
u_int	kl_n_shift = 32;
klinfo_t *kl_glass_console = NULL;

+#ifdef MULTIPROCESSOR
+struct cpu_hwinfo secondarycpu_hwinfo[MAXCPUS];
+#endif
+
void
kl_init(int ip35)
{
@@ -258,8 +262,24 @@ kl_first_pass_comp(klinfo_t *comp, void 
			bootcpu_hwinfo.clock = cpucomp->cpu_speed * 1000000;
			bootcpu_hwinfo.tlbsize = 64;
			bootcpu_hwinfo.type = (cpucomp->cpu_prid >> 8) & 0xff;
-		} else
+			bootcpu_hwinfo.nasid = comp->nasid;
+			bootcpu_hwinfo.physid = comp->physid;
+		} else {
+#ifdef MULTIPROCESSOR
+			int cpuid = ncpusfound;
+			secondarycpu_hwinfo[cpuid].c0prid = cpucomp->cpu_prid;
+			if (ip35)
+				secondarycpu_hwinfo[cpuid].c1prid = cpucomp->cpu_prid;
+			else
+				secondarycpu_hwinfo[cpuid].c1prid = cpucomp->cpu_fpirr;
+			secondarycpu_hwinfo[cpuid].clock = cpucomp->cpu_speed * 1000000;
+		        secondarycpu_hwinfo[cpuid].tlbsize = 64;
+			secondarycpu_hwinfo[cpuid].type = (cpucomp->cpu_prid >> 8) & 0xff;
+			secondarycpu_hwinfo[cpuid].nasid = comp->nasid;
+			secondarycpu_hwinfo[cpuid].physid = comp->physid;
+#endif
			ncpusfound++;
+		}
		break;

	case KLSTRUCT_MEMBNK: